LFSC3GA80E-7FN256I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LFSC3GA80E-7FN256I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Figure 2-7. Edge Clock Resources

SERDES

Architecture

LatticeSC/M Family Data Sheet

Bank 1

SERDES

Edge clock

Bank 5

Bank 4

Precision Clock Divider

Each set of edge clocks has four high-speed dividers associated with it. These are intended for generating a slower

speed system clock from the high-speed edge clock. The block operates in a DIV2 or DIV4 mode and maintains a

known phase relationship between the divided down clock and high-speed clock based on the release of its reset

signal. The clock dividers can be fed from selected PIOs, PLLs and routing. The clock divider outputs serve as pri-

mary clock sources. This circuit also generates an edge local set/reset (ELSR) signal which is fed to the PIOs via

the edge clock network and is used for the rest of the I/O gearing logic.

Figure 2-8. Clock Divider Circuit

Clock derived

from selected

PIOs, PLLs and

routing

LSR

S/R

S/R

S/R

S/R

Divided clock

ELSR

Register chain to synchronize LSR to clock input

Dynamic Clock Select (DCS)

The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and

outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is

2-9

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