LFSCM3GA115EP1-5FC1704C View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSCM3GA115EP1-5FC1704C Datasheet PDF : 237 Pages
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Lattice Semiconductor
Figure 2-17. PIC Diagram
TD
Architecture
LatticeSC/M Family Data Sheet
PIO A
Tristate
Register Block
IOLT0
DO
TO
OPOS0
ONEG0
OPOS1
ONEG1
OPOS2
ONEG2
OPOS3
ONEG3
Output
Register Block
PADA
"T"
DO
PURESPEED
I/O Buffer
INCK
INDD
INFF
IPOS0
INEG0
IPOS1
INEG1
IPOS2
INEG2
IPOS3
INEG3
RUNAIL
LOCK
DI
DI
Input
Register Block
(including
delay and
AIL elements*)
CLK
CE
LSR
GSRN
ELSR
ECLK
HCLKOUT
LCLKOUT
CEO
LSRO
GSR
LSRO
HCLKIN
LCLKIN
UPDATE
Control
Muxes
Update Block
POS Update
NEG Update
PIO B
PIO C
PIO D
PADB
“C”
PADC
“T”
PADD
“C”
*AIL only on A or C pads located on the left, right and bottom of the device.
The A/B PIOs on the left and the right of the device can be paired to form a differentiated driver. The A/B and C/D
PIOs on all sides of the device can be paired to form differential receivers. Either A or C PIOs on all sides except
the one on top also provide a connection to an adaptive input logic capability that facilitates the implementation of
2-16
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