LFSC3GA40E-7FF1020I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA40E-7FF1020I Datasheet PDF : 237 Pages
| |||
Lattice Semiconductor
Architecture
LatticeSC/M Family Data Sheet
Table 2-9. Supported Input Standards
Input Standard
Single Ended Interfaces
VREF (Nom.)
VCCIO1 (Nom.)
On-chip Termination
LVTTL333
—
3.3
None
LVCMOS 33, 25, 18, 15, 123
—
3.3/2.5/1.8/1.5/1.2 None
PCI33, PCIX33, AGP1X333
—
3.3
None
PCIX15
AGP2X33
0.75
1.32
1.52
None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
—
None
HSTL18_I, II
HSTL18_III, IV
HSTL15_I, II
HSTL15_III, IV
SSTL33_I, II
0.9
1.08
0.75
0.9
1.5
1.82
None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
1.82
None / VCCIO: 50
1.52
None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
1.52
None / VCCIO: 50
3.3
None
SSTL25_I, II
SSTL18_I, II
GTL+, GTL
Differential Interfaces
1.25
0.9
1.0 / 0.8
2.52
1.82
1.5 / 1.22
None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
None / VCCIO: 50
SSTL18D_I, II
SSTL25D_I, II
SSTL33D_I, II
—
1.82
None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,
220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
—
2.52
None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,
220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
—
3.3
None
HSTL15D_I, II
HSTL18D_I, II
LVDS
—
1.52
None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,
220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
—
1.82
None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150,
220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210
—
—
None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,
220, 240
Mini-LVDS
BLVDS25
—
—
None / Diff: 120, 150 / Diff to VCMT: 120, 150
—
—
None
MLVDS25
—
—
None
HYPT (Hyper Transport)
—
—
None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,
220, 240
RSDS
—
—
None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,
220, 240
LVPECL33
—
≤2.5
None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150,
220, 240
1. When not specified VCCIO can be set anywhere in the valid operating range.
2. VCCIO needed for on-chip termination to VCCIO/2 or VCCIO only. VCCIO is not specified for off-chip termination or VTT termination.
3. All ratioed input buffers and dedicated pin input buffers include hysteresis with a typical value of 50mV.
2-27
Share Link: 