LFSC3GA25E-6FCN1704C View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA25E-6FCN1704C Datasheet PDF : 237 Pages
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Lattice Semiconductor
Architecture
LatticeSC/M Family Data Sheet
Differential Input Termination
The LatticeSC device allows two types of differential termination. The first is a single resistor across the differential
inputs. The second is a center-tapped system where each input is terminated to the on-chip termination bus VCMT.
The VCMT bus is DC-coupled through an internal capacitor to ground.
Figure 2-29 shows the differential termination schemes and Table 2-9 shows the nominal values of the termination
resistors.
Figure 2-29. Differential Termination Scheme
Termination Type
Discrete Off-Chip Solution
Lattice On-Chip Solution
Differential termination
Zo
+
2Zo
-
Zo
OFF-chip
ON-chip
Zo
+
2Zo
-
Zo
OFF-chip
ON-chip
Differential and common
mode termination
Zo
GND
Zo
Zo
+
-
Zo
OFF-chip
ON-chip
Zo
Zo
VCMT
+
-
Zo
Zo
GND
OFF-chip
ON-chip
Calibration
There are two calibration sources that are associated with the termination scheme used in the LatticeSC devices:
• DIFFR – This pin occurs in each bank that supports differential drivers and must be connected through a
1K+/-1% resistor to ground if differential outputs are used. Note that differential drivers are not supported in
banks 1, 4 and 5.
• XRES – There is one of these pins per device. It is used for several functions including calibrating on-chip
termination. This pin should always be connected through a 1K+/-1% resistor to ground.
The LatticeSC devices support two modes of calibration:
• Continuous – In this mode the SC devices continually calibrate the termination resistances. Calibration hap-
pens several times a second. Using this mode ensures that termination resistances remain calibrated as
the silicon junction temperature changes.
• User Request – In this mode the calibration circuit operates continuously. However, the termination resistor
values are only updated on the assertion of the calibration_update signal available to the core logic.
For more information on calibration, refer to the details of additional technical documentation at the end of this data
sheet.
Hot Socketing
The LatticeSC devices have been carefully designed to ensure predictable behavior during power-up and power-
down. To ensure proper power sequencing, care must be taken during power-up and power-down as described
below. During power-up and power-down sequences, the I/Os remain in tristate until the power supply voltage is
high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within specified limits,
2-32
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