LFSC3GA80E-7FN256I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA80E-7FN256I Datasheet PDF : 237 Pages
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Lattice Semiconductor
Architecture
LatticeSC/M Family Data Sheet
define their own operation. With ispLEVER, the user can define the mode for each quad in a design. Nine modes
are currently supported by the ispLEVER design flow:
• 8-bit SERDES Only
• 10-bit SERDES Only
• SONET (STS-12/STS-48)
• Gigabit Ethernet
• Fibre Channel
• XAUI
• Serial RapidIO
• PCI-Express
• Generic 8b10b
flexiPCS Quad
The flexiPCS logic is arranged in quads containing logic for four independent full-duplex data channels. Each
device in the LatticeSC family has up to eight quads of flexiPCS logic. The LatticeSC Family Selection Guide table
on the first page of this data sheet contains the number of flexiPCS channels present on the chip. Note that in
some packages (particularly lower pin count packages), not all channels from all quads on a given device may be
bonded to package pins.
Each quad supports up to four channels of full-duplex data and can be programmed into any one of several proto-
col based modes. Each quad requires its own reference clock which can be sourced externally or from the FPGA
logic. The user can utilize between one and four channels in a quad, depending on the application.
Figure 2-30 shows an example of four flexiPCS quads in a LatticeSC device. Quads are labeled according to the
address of their software controlled registers.
Figure 2-30. LatticeSC flexiPCS
flexiPCS
Quad 360
High Speed
Serial Data
flexiPCS
Quad 361
High Speed
Serial Data
flexiPCS
Quad 3E1
High Speed
Serial Data
flexiPCS
Quad 3E0
High Speed
Serial Data
SERDES Interface
SERDES Interface
FPGA Logic I/Os
SERDES Interface
SERDES Interface
flexiPCS
Quad 360
PCS/FPGA
Interface
flexiPCS
Quad 361
PCS/FPGA
Interface
FPGA Logic
flexiPCS
Quad 3E1
PCS/FPGA
Interface
flexiPCS
Quad 3E0
PCS/FPGA
Interface
FPGA Logic I/Os
2-35
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