LFSC3GA25E-6FCN1704C View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LFSC3GA25E-6FCN1704C Datasheet PDF : 237 Pages
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Lattice Semiconductor
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
LatticeSC/M Internal Timing Parameters1
Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5%
-7
Parameter
Symbol
Description
Min. Max.
PFU Logic Mode Timing
tLUT4_PFU
tLUT5_PFU
tLSR_PFU
tSUM_PFU
CTOF_DEL
MTOOFX_DEL
LSR_DEL
M_SET
LUT4 delay (A to D inputs to F output)
LUT5 delay (inputs to output)
Set/Reset to output (asynchronous)
Clock to Mux (M0,M1) input setup
time
—
—
—
0.113
0.045
0.152
0.378
—
tHM_PFU
tSUD_PFU
tHD_PFU
tCK2Q_PFU
M_HLD
DIN_SET
DIN_HLD
REG_DEL
Clock to Mux (M0,M1) input hold time -0.041 —
Clock to D input setup time
0.072 —
Clock to D input hold time
-0.028 —
Clock to Q delay, D-type register
configuration
— 0.224
tLE2Q_PFU
tLD2Q_PFU
LTCH_DEL
TLTCH_DEL
Clock to Q delay latch configuration — 0.294
D to Q throughput delay when latch is
enabled
—
0.300
PFU Memory Mode Timing
tCORAM_PFU CLKTOF_DEL
tSUDATA_PFU DIN_SET
tHDATA_PFU DIN_HLD
tSUADDR_PFU WAD_SET
tHADDR_PFU WAD_HLD
tSUWREN_PFU WE_SET
tHWREN_PFU WE_HLD
PIC Timing
Clock to Output
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Write/Read Enable Setup Time
Write/Read Enable Hold Time
— 0.575
-0.024 —
0.075 —
-0.176 —
0.110 —
0.014 —
0.078 —
PIO Input/Output Buffer Timing
tIN_PIO
tOUT_PIO
tSUI_PIO
IN_DEL
DOPADI_DEL
DIN_SET
Input Buffer Delay(LVCMOS25)
Output Buffer Delay(LVCMOS25)
Input Register Setup Time (Data
Before Clock)
— 0.578
— 2.712
-0.156 —
tHI_PIO
DIN_HLD
Input Register Hold Time (Data after
Clock)
-0.267
—
tCOO_PIO
CK_DEL
Output Register Clock to Output
Delay
— 0.513
tSUCE_PIO CE_SET
Input Register Clock Enable Setup
Time
— 0.000
tHCE_PIO
CE_HLD
Input Register Clock Enable Hold
Time
— 0.129
tSULSR_PIO
tHLSR_PIO
tLE2Q_PIO
LSR_SET
LSR_HLD
CK_DEL
Set/Reset Setup Time
Set/Reset Hold Time
Input Register Clock to Q delay latch
configuration
0.057
-0.151
—
—
—
0.335
tLD2Q_PIO
DIN_DEL
Input Register D to Q throughput
delay when latch is enabled
— 0.578
-6
Min. Max.
— 0.050
— 0.172
— 0.426
0.131 —
-0.046 —
0.083 —
-0.032 —
— 0.252
— 0.331
— 0.338
— 0.649
-0.026 —
0.084 —
-0.196 —
0.124 —
0.019 —
0.086 —
— 0.661
— 3.027
-0.175 —
-0.306 —
— 0.571
— 0.000
— 0.145
0.060 —
-0.159 —
— 0.372
— 0.647
-5
Min. Max.
— 0.054
— 0.192
— 0.474
0.148 —
-0.052 —
0.094 —
-0.035 —
— 0.279
— 0.367
— 0.376
— 0.724
-0.027 —
0.094 —
-0.215 —
0.138 —
0.024 —
0.094 —
— 0.744
— 3.395
-0.194 —
-0.345 —
— 0.639
— 0.000
— 0.161
0.063 —
-0.169 —
— 0.410
— 0.717
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-17
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