Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Address
0xE520
Register
Name
VNOM
R/W1, 2
R/W
Bit
Length2
24
Bit Length During
Communication2, 3
32 ZP
Type2, 4
S
Default
Value2
0x000000
0xE521 to Reserved
0xE52F
N/A N/A
0xE530 IARMS_LRIP R
24
0xE531 VARMS_LRIP R
24
0xE532 IBRMS_LRIP R
24
0xE533 VBRMS_LRIP R
24
0xE534 ICRMS_LRIP R
24
0xE535 VCRMS_LRIP R
24
0xE536 INRMS_LRIP R
24
0xE537 to Reserved
0xE5FE
N/A N/A
0xE5FF LAST_
R
32
RWDATA_32
0xE600 PHSTATUS R
16
0xE601 ANGLE0
R
16
0xE602 ANGLE1
R
16
0xE603 ANGLE2
R
16
0xE604 to Reserved
0xE606
N/A N/A
0xE607 Period
R
16
0xE608 PHNOLOAD R
16
0xE609 to Reserved
0xE60B
N/A N/A
0xE60C LINECYC
R/W 16
0xE60D ZXTOUT
R/W 16
0xE60E COMPMODE R/W 16
0xE60F Gain
R/W 16
0xE610 CFMODE
R/W 16
0xE611 CF1DEN
R/W 16
0xE612 CF2DEN
R/W 16
0xE613 CF3DEN
R/W 16
0xE614 APHCAL
R/W 10
0xE615 BPHCAL
R/W 10
0xE616 CPHCAL
R/W 10
0xE617 PHSIGN
R
16
0xE618 CONFIG
R/W 16
0xE619 to Reserved
0xE6FD
N/A N/A
0xE6FE LAST_ADDR R
16
0xE6FF LAST_
R
16
RWDATA_16
0xE700 MMODE
R/W 8
N/A
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
N/A
32
16
16
16
16
N/A
16
16
N/A
16
16
16
16
16
16
16
16
16 ZP
16 ZP
16 ZP
16
16
N/A
16
N/A
N/A
S
N/A
S
N/A
S
N/A
S
N/A
S
N/A
S
N/A
S
N/A
N/A
N/A
U
N/A
U
N/A
U
N/A
U
N/A
U
N/A
N/A
N/A
U
N/A
U
N/A
N/A
N/A
U
0xFFFF
U
0xFFFF
U
0x01FF
U
0x0000
U
0x0E88
U
0x0000
U
0x0000
U
0x0000
S
0x0000
S
0x0000
S
0x0000
U
N/A
U
0x0000
N/A
N/A
U
N/A
16
U
N/A
8
U
0x1C
Rev. C | Page 81 of 96
Description
Nominal phase voltage rms used in the
alternative computation of the apparent
power. When the VNOMxEN bit is set, the
applied voltage input in the correspond-
ing phase is ignored and all corresponding
rms voltage instances are replaced by the
value in the VNOM register.
For proper operation, do not write to
these memory locations.
1.024 sec average of Phase A current rms.
1.024 sec average of Phase A voltage rms.
1.024 sec average of Phase B current rms.
1.024 sec average of Phase B voltage rms.
1.024 sec average of Phase C current rms.
1.024 sec average of Phase C voltage rms.
1.024 sec average of the neutral current
rms.
For proper operation, do not write to
these memory locations.
Contains the data from the last successful
32-bit register communication.
Phase peak register. See Table 38.
Time Delay 0. See the Time Interval Between
Phases section for more information.
Time Delay 1. See the Time Interval Between
Phases section for more information.
Time Delay 2. See the Time Interval Between
Phases section for more information.
For proper operation, do not write to
these memory locations.
Network line period.
Phase no load register. See Table 39.
For proper operation, do not write to
these memory locations.
Line cycle accumulation mode count.
Zero-crossing timeout count.
Computation-mode register. See Table 40.
PGA gains at ADC inputs. See Table 41.
CFx configuration register. See Table 42.
CF1 denominator.
CF2 denominator.
CF3 denominator.
Phase calibration of Phase A. See Table 43.
Phase calibration of Phase B. See Table 43.
Phase calibration of Phase C. See Table 43.
Power sign register. See Table 44.
ADE7878A configuration register. See
Table 45.
For proper operation, do not write to
these memory locations.
The address of the register successfully
accessed during the last read/write
operation.
Contains the data from the last successful
16-bit register communication.
Measurement mode register. See Table 47.