STAP16DPPS05 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STAP16DPPS05
STMicroelectronics
STAP16DPPS05 Datasheet PDF : 29 Pages
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STAP16DPPS05
Timing diagrams
5
Timing diagrams
Clock LE/DM1 OE/DM2
Table 9: Truth table
Serial-IN
OUT0 ............. OUT7 ................
OUT15
SDO
_|¯
H
_|¯
L
_|¯
H
¯|_
X
¯|_
X
L
Dn
L
Dn + 1
L
Dn + 2
L
Dn + 3
H
Dn + 3
Dn ..... Dn - 7 ..... Dn -15
No change
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn + 2 ..... Dn - 5 ..... Dn -13
OFF
Dn - 15
Dn - 14
Dn - 13
Dn - 13
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L.
Figure 7: Timing diagram
Latch and output enable terminals are level-sensitive and are not synchronized
with rising or falling edge of LE/DM1 signal. When LE/DM1 terminal is low level,
the latch circuit holds previous set of data. When LE/DM1 terminal is high level,
the latch circuit refreshes new set of data from SDI chain. When OE/DM2
terminal is at low level, the output terminals Out 0 to Out 15 respond to data in the
latch circuits, either ‘1’ ON or ‘0’ OFF. When OE/DM2 terminal is at high level,
all output terminals are switched OFF.
DocID024306 Rev 7
11/29
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