STM32F051R4U7(2012) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM32F051R4U7
(Rev.:2012)
(Rev.:2012)
STMicroelectronics
STM32F051R4U7 Datasheet PDF : 104 Pages
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Electrical characteristics
STM32F051x
Table 66. SPI characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
tsu(NSS)(1)
th(NSS)(1)
tw(SCKH)(1)
tw(SCKL)(1)
NSS setup time
NSS hold time
SCK high and low time
Slave mode
Slave mode
Master mode, fPCLK = 36 MHz,
presc = 4
4Tpclk
-
2Tpclk + 10
-
Tpclk/2 -2 Tpclk/2 + 1
tsu(MI) (1)
tsu(SI)(1)
Data input setup time
Master mode
Slave mode
4
-
5
-
th(MI) (1)
th(SI)(1)
ta(SO)(1)(2)
tdis(SO)(1)(3)
tv(SO) (1)
tv(MO)(1)
th(SO)(1)
th(MO)(1)
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Master mode
Slave mode
Slave mode, fPCLK = 20 MHz
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
4
5
0
0
-
-
11.5
2
-
-
ns
3Tpclk
18
22.5
6
-
-
DuCy(SCK)
SPI slave input clock duty
cycle
Slave mode
25
75
%
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
Figure 26. SPI timing diagram - slave mode and CPHA = 0
NSS input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
tSU(NSS)
tc(SCK)
tw(SCKH)
tw(SCKL)
ta(SO)
MISO
OUT P UT
MOSI
I NPUT
tsu(SI)
tv(SO)
MS B O UT
M SB IN
th(SI)
th(SO)
BI T6 OUT
B I T1 IN
th(NSS)
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
LSB IN
ai14134c
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Doc ID 022265 Rev 3
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