AT91SAM9G46B-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT91SAM9G46B-CU

SMART ARM-based Embedded MPU

Atmel Corporation 

The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS)

which defines:

 Constraints on the use of registers

 Stack conventions

 Argument passing and result return

For more details, refer to ARM Software Development Kit.

The Thumb state register set is a subset of the ARM state set. The programmer has direct access to:

 Eight general-purpose registers r0–r7

 Stack pointer, SP

 Link register, LR (ARM r14)

 PC

 CPSR

There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S

Technical Reference Manual, revision r1p2 page 2-12).

8.4.7.1 Status Registers

The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status

registers:

 hold information about the most recently performed ALU operation

 control the enabling and disabling of interrupts

 set the processor operation mode

Figure 8-2. Status Register Format

31 30 29 28 27

24

NZ CVQ

J

Reserved

765

I FT

0

Mode

Jazelle state bit

Reserved

Sticky Overflow

Overflow

Carry/Borrow/Extend

Zero

Negative/Less than

Mode bits

Thumb state bit

FIQ disable

IRQ disable

Figure 8-2 shows the status register format, where:

 N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags

 The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD,

QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations.

The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR

instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.

 The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:

̶ J = 0: The processor is in ARM or Thumb state, depending on the T bit

̶ J = 1: The processor is in Jazelle state.

 Mode: five bits to encode the current processor mode

38 SAM9G46 Series [DATASHEET]

Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15

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