AT91SAM9G20-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT91SAM9G20-CU Datasheet PDF : 42 Pages
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Figure 9-2.
Clock Generator Block Diagram
OSCSEL
XIN32
XOUT32
Clock Generator
On Chip
RC OSC
Slow Clock
Oscillator
XIN
XOUT
Main
Oscillator
PLL and
Divider A
PLL and
Divider B
Slow Clock
SLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
PLLB Clock
PLLBCK
Status Control
Power
Management
Controller
9.5 Power Management Controller
• Provides:
– the Processor Clock PCK
– the Master Clock MCK, in particular to the Matrix and the memory interfaces.The
MCK divider can be 1,2,4,6
– the USB Device Clock UDPCK
– independent peripheral clocks, typically at the frequency of MCK
– 2 programmable clock outputs: PCK0, PCK1
• Five flexible operating modes:
– Normal Mode, processor and peripherals running at a programmable frequency
– Idle Mode, processor stopped waiting for an interrupt
– Slow Clock Mode, processor and peripherals running at low frequency
– Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency,
processor stopped waiting for an interrupt
– Backup Mode, Main Power Supplies off, VDDBU powered by a battery
26 AT91SAM9G20 Summary
6384CS–ATARM–11-Mar-09
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