AT91SAM7S64C-AU View Datasheet(PDF) - Atmel Corporation
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AT91SAM7S64C-AU Datasheet PDF : 775 Pages
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22. Peripheral DMA Controller (PDC)
22.1
Overview
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART,
USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Controller avoids processor
intervention and removes the processor interrupt-handling overhead. This significantly reduces the number of
clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and
makes it more power efficient.
The PDC channels are implemented in pairs, each pair being dedicated to a particular peripheral. One channel in
the pair is dedicated to the receiving channel and one to the transmitting channel of each UART, USART, SSC and
SPI.
The user interface of a PDC channel is integrated in the memory space of each peripheral. It contains:
• two 32-bit memory pointer registers (send and receive)
• two 16-bit transfer count registers (send and receive)
• two 32-bit registers for next memory pointer (send and receive)
• two 16-bit registers for next transfer count (send and receive)
The peripheral triggers PDC transfers using transmit and receive signals. When the programmed data is trans-
ferred, an end of transfer interrupt is generated by the corresponding peripheral.
22.2 Block Diagram
Figure 22-1. Block Diagram
Peripheral
Peripheral DMA Controller
THR
PDC Channel 0
RHR
Control
PDC Channel 1
Control
Status & Control
Memory
Controller
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
151
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