AT91SAM7S64C-AU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT91SAM7S64C-AU Datasheet PDF : 775 Pages
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25.9.9 PMC Clock Generator PLL Register
Register Name:
CKGR_PLLR
Access Type:
Read-write
31
30
29
28
27
26
25
24
–
–
USBDIV
–
MUL
23
22
21
20
19
18
17
16
MUL
15
14
13
12
11
10
9
8
OUT
PLLCOUNT
7
6
5
4
3
2
1
0
DIV
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
• DIV: Divider
DIV
0
1
2 - 255
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIV.
• PLLCOUNT: PLL Counter
Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• OUT: PLL Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1.
• USBDIV: Divider for USB Clock (Does not Pertain to SAM73S2/16
USBDIV
Divider for USB Clock(s)
0
0
Divider output is PLL clock output.
0
1
Divider output is PLL clock output divided by 2.
1
0
Divider output is PLL clock output divided by 4.
1
1
Reserved.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
208
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