AT91SAM7S64C-AU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT91SAM7S64C-AU

AT91SAM ARM-based Flash MCU

Atmel Corporation 

When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit

rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error

bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the sta-

tus register to clear the OVRES bit.

When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in

the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the

last reset, all bits are transmitted low, as the Shift Register resets at 0.

When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If

new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the

SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the

TDRE bit rises. This enables frequent updates of critical variables with single transfers.

Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to

be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Regis-

ter, the Shift Register is not modified and the last received character is retransmitted.

Figure 28-9 shows a block diagram of the SPI when operating in Slave Mode.

Figure 28-9. Slave Mode Functional Block Diagram

SPCK

NSS

MOSI

SPIEN

SPIENS

SPIDIS

SPI_CSR0

BITS

NCPHA

CPOL

LSB

SPI

Clock

SPI_RDR

RD

RDRF

OVRES

Shift Register

MSB

MISO

SPI_TDR

TD

TDRE

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

280

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