SAM7X512/256/128 Summary
Table 12-2. Revision History
Doc. Rev
6120ES
6120FS
6120GS
Comments
“Features”,TWI updated to include Atmel TWI compatibility with I2C Standard.
Section 10.8 ”Two-wire Interface”, updated.
Section 7.4 ”Peripheral DMA Controller”, added PDC priority list.
Section 10.11 ”Timer Counter”, The TC has Two output compare or one input capture per channel.
Section 10.15 ”Analog-to-Digital Converter”, INL and DNL updated.
Table 3-1, “Signal Description List” footnote added to JTAGSEL, ERASE and TST pin comments.
Section 6.1 ”JTAG Port Pins”, Section 6.2 ”Test Pin” and Section 6.4 ”ERASE Pin”, updated.
Section 8.4.3 ”Internal Flash”, updated: “At any time, the Flash is mapped... if GPNVM bit 2 is set and
before the Remap Command.”
Figure 9-1,”System Controller Block Diagram”, RTT is reset by power_on_reset.
”Features”, ”Debug Unit (DBGU)”, added ”Mode for General Purpose 2-wire UART Serial
Communication”
Section 12. ”Ordering Information”, MLR B parts added to ordering information.
Section 12. ”Ordering Information”, MLR C parts added to ordering information
Section 9.5 ”Debug Unit”
“Chip ID Registers”, Chip IDs updated with reference to MRL A, B or C.
Product Series Naming Convention:
Except for part ordering and library references, AT91 prefix dropped from most nomenclature.
AT91SAM7X becomes SAM7X.
Change
Request
Ref.
4247
4774
4210
4007
5064
5850
5223
5846
6064
7371
rfo
43
6120GS–ATARM–07-Apr-11