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STM8S007C8T6TR(2015) View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
STM8S007C8T6TR Datasheet PDF : 92 Pages
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Block diagram
3
Block diagram
STM8S007C8
Figure 1. STM8S007C8 value line block diagram
Reset
Single wire
debug interf.
400 Kbit/s
10 Mbit/s
LIN master
SPI emul.
Master/slave
autosynchro
16 channels
1/2/4 kHz
beep
Reset block
Reset
POR
BOR
Clock controller
Detector
XTAL 1-24 MHz
RC int. 16 MHz
RC int. 128 kHz
Clock to peripherals and core
STM8 core
Debug/SWIM
I2C
SPI
UART1
UART3
ADC2
Beeper
Window WDG
Independent WDG
64 Kbytes high
density program Flash
128 bytes
data EEPROM
6 Kbytes RAM
Boot ROM
16-bit advanced control
timer (TIM1)
16-bit general purpose
timers (TIM2, TIM3)
8-bit basic timer
(TIM4)
Up to
4 CAPCOM
channels
+ 3 complementary
outputs
Up to
5 CAPCOM
channels
AWU timer
10/92
DocID022171 Rev 5

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