STM8S007C8T6TR(2015) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM8S007C8T6TR
(Rev.:2015)
(Rev.:2015)
STMicroelectronics
STM8S007C8T6TR Datasheet PDF : 92 Pages
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Pinouts and pin descriptions
STM8S007C8
Table 5. STM8S007C8 pin description (continued)
Input
Output
Pin name
Default
alternate
function
Alternate
function
after remap
[option bit]
33 PC6/SPI_MOSI
SPI master
I/O X X X HS O3 X X Port C6 out/ï€
slave in
34 PC7/SPI_MISO
I/O X
X
X
HS O3 X
X
Port C7
SPI master in/
slave out
35 PG0
I/O X X
O1 X X Port G0
36 PG1
I/O X X
O1 X X Port G1
37 PE3/TIM1_BKIN I/O X X X
38 PE2/I2C_SDA
I/O X
X
39 PE1/I2C_SCL
I/O X
X
O1 X
X
Port E3
Timer 1 - ï€
break input
O1 T(2)
Port E2 I2C data
O1 T(2)
Port E1 I2C clock
40 PE0/CLK_CCO
I/O X
X
X
HS O3 X
X
Port E0
Configurable
clock output
41 PD0/TIM3_CH2
I/O X X
X
HS O3 X
X
Port D0
Timer 3 -
channel 2
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
42 PD1/SWIM(3)
I/O X
X
X
HS O4 X
X
Port D1
SWIM data
interface
43 PD2/TIM3_CH1
I/O X X
X
HS O3 X
X
Port D2
Timer 3 -
channel 1
TIM2_CH3
[AFR1]
44 PD3/TIM2_CH2
I/O X X
X
HS O3 X
X
Port D3
Timer 2 -
channel 2
ADC_ETR
[AFR0]
45
PD4/TIM2_CH1/B
EEP
I/O
X
X
X
HS O3 X
X
Port D4
Timer 2 -
channel 1
BEEP output
[AFR7]
46 PD5/ UART3_TX I/O X X X
O1 X
X
Port D5
UART3 data
transmit
47
PD6/
UART3_RX(1)
I/O X X X
O1 X
X
Port D6
UART3 data
receive
48 PD7/TLI
I/O X X X
O1 X
X
Port D7
Top level
interrupt
1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are
pulled up as part of the bootloader activation process and returned to the floating state before a return from
the bootloader.
2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection
diode to VDD are not implemented).
3. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.
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DocID022171 Rev 5
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