Memory and register map
STM8S105x4/6
Table 6. Flash, data EEPROM and RAM boundary address
Memory area
Size (byte)
Start address
End address
Flash program memory
32 K
16 K
0x00 8000
0x00 8000
0x00 FFFF
0x00 BFFF
RAM
2K
0x00 0000
0x00 07FF
Data EEPROM
1024
0x00 4000
0x00 43FF
6.2
Register map
6.2.1 I/O port hardware register map
Address
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
Block
Port A
Port B
Port C
Port D
Table 7. I/O port hardware register map
Register label
Register name
PA_ODR
Port A data output latch register
PA_IDR
Port A input pin value register
PA_DDR
Port A data direction register
PA_CR1
Port A control register 1
PA_CR2
Port A control register 2
PB_ODR
Port B data output latch register
PB_IDR
Port B input pin value register
PB_DDR
Port B data direction register
PB_CR1
Port B control register 1
PB_CR2
Port B control register 2
PC_ODR
Port C data output latch register
PB_IDR
Port C input pin value register
PC_DDR
Port C data direction register
PC_CR1
Port C control register 1
PC_CR2
Port C control register 2
PD_ODR
Port D data output latch register
PD_IDR
Port D input pin value register
PD_DDR
Port D data direction register
PD_CR1
Port D control register 1
PD_CR2
Port D control register 2
Reset status
0x00
0xXX(1)
0x00
0x00
0x00
0x00
0xXX(1)
0x00
0x00
0x00
0x00
0xXX(1)
0x00
0x00
0x00
0x00
0xXX(1)
0x00
0x02
0x00
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DocID14771 Rev 15