STM8S105xx
Memory and register map
Address Block Register label Register name
0x00
50C6
CLK_CKDIVR Clock divider register
Reset
status
0x18
0x00
50C7
CLK_PCKENR1 Peripheral clock gating register 1
0xFF
0x00
50C8
CLK_CSSR
Clock security system register
0x00
0x00
50C9
CLK_CCOR
Configurable clock control register 0x00
0x00
50CA
CLK_PCKENR2 Peripheral clock gating register 2
0xFF
0x00
50CB
CLK_CANCCR CAN clock control register
0x00
0x00
50CC
CLK_HSITRIMR HSI clock calibration trimming register xx
0x00
50CD
CLK_SWIMCCR SWIM clock control register
x0
0x00
50CE to
0x00
50D0
Reserved area (3 bytes)
0x00
50D1
WWDG WWDG_CR
WWDG control register
0x7F
0x00
50D2
WWDG_WR
WWDR window register
0x7F
0x00
50D3 to
0x00
50DF
Reserved area (13 bytes)
DocID14771 Rev 9
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