STM8S105xx
Memory and register map
Address Block Register label Register name
Reset
status
0x00
5310
TIM2_CCR1L TIM2 capture/ compare register 1 low 0x00
0x00
5311
TIM2_CCR2H TIM2 capture/ compare reg. 2 high 0x00
0x00
5312
TIM2_CCR2L TIM2 capture/ compare register 2 low 0x00
0x00
5313
TIM2_CCR3H TIM2 capture/ compare register 3 high 0x00
0x00
5314
TIM2_CCR3L TIM2 capture/ compare register 3 low 0x00
0x00
5315 to
0x00
531F
Reserved area (11 bytes)
0x00
5320
TIM3
TIM3_CR1
TIM3 control register 1
0x00
0x00
5321
TIM3_IER
TIM3 interrupt enable register
0x00
0x00
5322
TIM3_SR1
TIM3 status register 1
0x00
0x00
5323
TIM3_SR2
TIM3 status register 2
0x00
0x00
5324
TIM3_EGR
TIM3 event generation register
0x00
0x00
5325
TIM3_CCMR1
TIM3 capture/ compare mode
register 1
0x00
0x00
5326
TIM3_CCMR2
TIM3 capture/ compare mode
register 2
0x00
DocID14771 Rev 9
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