PIC16(L)F1503
TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
Clock
Source
ADCS<2:0
>
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
FRC
Legend:
Note:
000
100 ns
125 ns
250 ns
500 ns
2.0 s
100
200 ns
250 ns
001
400 ns
500 ns
101
800 ns
1.0 s
010
1.6 s
2.0 s
110
3.2 s
4.0 s
x11
1.0-6.0 s
1.0-6.0 s
Shaded cells are outside of recommended range.
500 ns
1.0 s
2.0 s
4.0 s
8.0 s
1.0-6.0 s
1.0 s
2.0 s
4.0 s
8.0 s
16.0 s
1.0-6.0 s
4.0 s
8.0 s
16.0 s
32.0 s
64.0 s
1.0-6.0 s
The TAD period when using the FRC clock source can fall within a specified range, (see TAD parameter).
The TAD period when using the FOSC-based clock source can be configured for a more precise TAD period.
However, the FRC clock source must be used when conversions are to be performed with the device in
Sleep mode.
FIGURE 15-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
Rev. 10-000035A
7/30/2013
TACQ
THCD
TAD1
TAD2
b9
TAD3 TAD4
b8
b7
Conversion Starts
Holding capacitor disconnected
from analog input (THCD).
Set GO bit
Enable ADC (ADON bit)
and
Select channel (ACS bits)
TAD5 TAD6
b6
b5
TAD7 TAD8
b4
b3
TAD9 TAD10 TAD11
b2
b1
b0
On the following cycle:
ADRESH:ADRESL is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is reconnected to analog input.
2011-2015 Microchip Technology Inc.
DS40001607D-page 115