PIC16F1503T-I View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1503T-I

14-Pin Flash, 8-Bit Microcontrollers

Microchip Technology 

PIC16(L)F1503

21.6 I2C MASTER MODE

Master mode is enabled by setting and clearing the

appropriate SSPM bits in the SSPxCON1 register and

by setting the SSPEN bit. In Master mode, the SDAx

and SCKx pins must be configured as inputs. The

MSSP peripheral hardware will override the output

driver TRIS controls when necessary to drive the pins

low.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop con-

ditions. The Stop (P) and Start (S) bits are cleared from

a Reset or when the MSSPx module is disabled. Con-

trol of the I2C bus may be taken when the P bit is set,

or the bus is idle.

In Firmware Controlled Master mode, user code

conducts all I2C bus operations based on Start and

Stop bit condition detection. Start and Stop condition

detection is the only active circuitry in this mode. All

other communication is done by the user software

directly manipulating the SDAx and SCLx lines.

The following events will cause the SSPx Interrupt Flag

bit, SSPxIF, to be set (SSPx interrupt, if enabled):

• Start condition detected

• Stop condition detected

• Data transfer byte transmitted/received

• Acknowledge transmitted/received

• Repeated Start generated

Note 1: The MSSPx module, when configured in

I2C Master mode, does not allow queue-

ing of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPxBUF register

to initiate transmission before the Start

condition is complete. In this case, the

SSPxBUF will not be written to and the

WCOL bit will be set, indicating that a

write to the SSPxBUF did not occur

2: When in Master mode, Start/Stop detec-

tion is masked and an interrupt is gener-

ated when the SEN/PEN bit is cleared and

the generation is complete.

21.6.1 I2C MASTER MODE OPERATION

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDAx, while SCLx outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (seven bits) and the Read/Write (R/W)

bit. In this case, the R/W bit will be logic ‘0’. Serial data

is transmitted eight bits at a time. After each byte is

transmitted, an Acknowledge bit is received. Start and

Stop conditions are output to indicate the beginning

and the end of a serial transfer.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(seven bits) and the R/W bit. In this case, the R/W bit

will be logic ‘1’. Thus, the first byte transmitted is a 7-bit

slave address followed by a ‘1’ to indicate the receive

bit. Serial data is received via SDAx, while SCLx out-

puts the serial clock. Serial data is received eight bits at

a time. After each byte is received, an Acknowledge bit

is transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

A Baud Rate Generator is used to set the clock

frequency output on SCLx. See Section21.7 “Baud

Rate Generator” for more detail.

DS40001607D-page 186

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