PIC16F1503T-I View Datasheet(PDF) - Microchip Technology
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PIC16F1503T-I Datasheet PDF : 352 Pages
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PIC16(L)F1503
21.7 BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator avail-
able for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPxADD register (Register 21-6).
When a write occurs to SSPxBUF, the Baud Rate Gen-
erator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in Figure 21-40 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP is
being operated in.
Table 21-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
EQUATION 21-1:
FCLOCK = ---S---S----P----x---A--F--D--O--D-S---C--+------1--------4----
FIGURE 21-40: BAUD RATE GENERATOR BLOCK DIAGRAM
Rev. 10-000112A
7/30/2013
SSPM <3:0> 4
SSPM <3:0> 4
SCLx
Reload
Control
SSPxADD<7:0>
8
Reload
8
FOSC/2
BRG Down Counter
SSPxCLK
Note:
Values of 0x00, 0x01 and 0x02 are not valid
for SSPxADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 21-4: MSSP CLOCK RATE W/BRG
Note:
FOSC
FCY
BRG Value
FCLOCK
(Two Rollovers of BRG)
16 MHz
4 MHz
09h
400 kHz
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
Refer to the I/O port electrical and timing specifications in Table 28-9 and Figure 28-7 to ensure the system
is designed to support the I/O timing requirements.
DS40001607D-page 202
2011-2015 Microchip Technology Inc.
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