PIC16F1503T-I View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1503T-I

14-Pin Flash, 8-Bit Microcontrollers

Microchip Technology 

PIC16(L)F1503

23.1 CLCx Setup

Programming the CLCx module is performed by config-

uring the four stages in the logic signal flow. The four

stages are:

• Data selection

• Data gating

• Logic function selection

• Output polarity

Each stage is setup at run time by writing to the corre-

sponding CLCx Special Function Registers. This has

the added advantage of permitting logic reconfiguration

on-the-fly during program execution.

23.1.1 DATA SELECTION

There are 16 signals available as inputs to the configu-

rable logic. Four 8-input multiplexers are used to select

the inputs to pass on to the next stage. The 16 inputs to

the multiplexers are arranged in groups of four. Each

group is available to two of the four multiplexers, in

each case, paired with a different group. This arrange-

ment makes possible selection of up to two from a

group without precluding a selection from another

group.

Data selection is through four multiplexers as indicated

on the left side of Figure 23-2. Data inputs in the figure

are identified by a generic numbered input name.

Table 23-1 correlates the generic input name to the

actual signal for each CLC module. The columns labeled

lcxd1 through lcxd4 indicate the MUX output for the

selected data input. D1S through D4S are abbreviations

for the MUX select input codes: LCxD1S<2:0> through

LCxD4S<2:0>, respectively. Selecting a data input in a

column excludes all other inputs in that column.

Data inputs are selected with CLCxSEL0 and

CLCxSEL1 registers (Register 23-3 and Register 23-5,

respectively).

Note: Data selections are undefined at power-up.

TABLE 23-1:

Data Input

LCx_in[0]

LCx_in[1]

LCx_in[2]

LCx_in[3]

LCx_in[4]

LCx_in[5]

LCx_in[6]

LCx_in[7]

LCx_in[8]

LCx_in[9]

LCx_in[10]

LCx_in[11]

LCx_in[12]

LCx_in[13]

LCx_in[14]

LCx_in[15]

CLCx DATA INPUT SELECTION

lcxd1

D1S

000

001

010

011

100

101

110

111

—

—

—

—

—

—

—

—

lcxd2

D2S

—

—

—

—

000

001

010

011

100

101

110

111

—

—

—

—

lcxd3

D3S

—

—

—

—

—

—

—

—

000

001

010

011

100

101

110

111

lcxd4

D4S

100

101

110

111

—

—

—

—

—

—

—

—

000

001

010

011

CLC 1

CLC1IN0

CLC1IN1

C1OUT_sync

C2OUT_sync

FOSC

T0_overflow

T1_overflow

T2_match

LC1_out

LC2_out

Reserved

Reserved

NCO1_out

HFINTOSC

PWM3_out

PWM4_out

CLC 2

CLC2IN0

CLC2IN1

C1OUT_sync

C2OUT_sync

FOSC

T0_overflow

T1_overflow

T2_match

LC1_out

LC2_out

Reserved

Reserved

LFINTOSC

FRC

PWM1_out

PWM2_out

 2011-2015 Microchip Technology Inc.

DS40001607D-page 215

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