PIC16(L)F1503
REGISTER 7-4:
U-0
—
bit 7
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0/0
CLC2IE
R/W-0/0
CLC1IE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
bit 0
Unimplemented: Read as ‘0’
CLC2IE: Configurable Logic Block 2 Interrupt Enable bit
1 = Enables the CLC 2 interrupt
0 = Disables the CLC 2 interrupt
CLC1IE: Configurable Logic Block 1 Interrupt Enable bit
1 = Enables the CLC 1 interrupt
0 = Disables the CLC 1 interrupt
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
2011-2015 Microchip Technology Inc.
DS40001607D-page 67