ZPSD311-B-90UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ZPSD311-B-90UI Datasheet PDF : 85 Pages
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PSD3XX Family
10.0
I/O Port
Functions
(cont.)
10.2.2 Port A (PA0-PA7) in Non-Multiplexed Address/Data Mode
In this mode, Port A becomes the low-order data bus byte of the chip. When reading an
internal location, data is presented on Port A pins to the MCU. When writing to an internal
location, data present on Port A pins from the MCU is written to the desired location.
Figure 5A. Port A Pin Structure
I
N
READ PIN
T
E
R
READ DATA
N
A
CMOS / OD(1)
L
MCU
WRITE DATA
A
CK
I/O
OUT
PORT A PIN
D
D
) R
t(s /
D
c A
u T
d A
Pro t(s) B
U
te c S
le du A
so ro D
0
b P /
A
- O te D
7
) le RESET
DFF
DR
ALE
G
LATCH
D
R
READ DIR
D DIR
WRITE DIR CK FF
R
LATCHED
ADDR OUT
ADn/ Dn
MUX
CONTROL
ENABLE
ct(s bso NOTE: 1. CMOS/OD determines whether the output is open drain or CMOS.
du - O Figure 5B. Port A Track Mode
Pro t(s)CONTROL
te c DECODER
INTERNAL
READ
sole rodu WR or R/W
RD / E
Ob te P AD0–AD7
Obsole ALE or AS
CSADIN
INTERNAL
ALE
I
O
PA0 – PA7
CSADOUT1
AD8– AD15
A11– A15
LATCH
PAD
CSADOUT2 (1)
A16 – A19
NOTE: 1. The expression for CSADOUT2 must include the following write operation cycle signals:
For CRRWR = 0, CSADOUT2 must include WR = 0.
For CRRWR = 1, CSADOUT2 must include E = 1 and R/W = 0.
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