ZPSD311V-B-20UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ZPSD311V-B-20UI Datasheet PDF : 85 Pages
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PSD3XX Family
12.0
Control Signals
(cont.)
12.5 A19/CSI
This pin is configured using PSDsoft to be either a chip select for the entire PSD device or
an additional PAD input. If your MCU can generate a chip-select signal, and you wish to
save power, use the PSD chip select feature. Otherwise, use this pin as an address or logic
input.
t When configured as CSI (active-low PSD chip select): a low on this pin keeps the PSD
in normal operation. However, when a high is detected on the pin, the PSD
enters Power-down Mode. See Tables 7A and 7B for information on signal states
during Power-down Mode. See section 16 for details about the reduction of power
consumption.
t When configured as A19, the pin can be used as an additional input to the PADs.
It can be used for address or logic. It can also be ALE/AS dependent or a transparent
input, which is determined by your PSDsoft design file. In A19 mode, the PSD is always
) enabled.
ct(s Table 7A. Signal States During Power-Down Mode
du Port
Configuration Mode(s)
Pro t(s) AD0–A0/AD15/A15
All
MCU I/O
lete uc Port Pins PA0–PA7
Tracking AD0/A0-AD7/A7
so rod Latched Address Out
b P MCU I/O
- O te Port Pins PB0–PB7
Chip Select Outputs, CS0–CS7, CMOS
) le Chip Select Outputs, CS0–CS7, Open Drain
ct(s bso Port Pins PC0–PC2
Address or Logic Inputs, A16-A18
Chip Select Outputs, CS8–CS10, CMOS only
State
Input (Hi-Z)
Unchanged
Input (Hi-Z)
Logic 1
Unchanged
Logic 1
Hi-Z
Input (Hi-Z)
Logic 1
rodu ) - O Table 7B. Internal States During Power-down
lete P uct(s Component
so rod PAD A and PAD B
Ob olete PAll registers in CSIOPORT
s address space, including:
Ob Direction
Internal Signal
CS0–CS10
CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
ES0-ES7, RS0
N/A
Internal Signal State
During Power-Down
Logic 1 (inactive)
Logic 0 (inactive)
Data
Page
All unchanged
PMR (turbo bit, ZPSD only)
NOTE: N/A = Not Applicable
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