ZPSD311-B-90UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ZPSD311-B-90UI Datasheet PDF : 85 Pages
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PSD3XX Family
12.0
Control Signals
(cont.)
12.6 Reset Input
This is an asynchronous input to initialize the PSD device.
Refer to tables 8A and 8B for information on device status during and after reset.
The standard-voltage PSD3XX and ZPSD3XX (non-V) devices require a reset input that
is asserted for at least 100 nsec. The PSD will be functional immediately after reset is
de-asserted. For these standard-voltage devices, the polarity of the reset input signal is
programmable using PSDsoft (active-high or active-low), to match the functionality of your
MCU reset.
Note: It is not recommended to drive the reset input of the MCU and the reset input of the
PSD with a simple RC circuit between power on ground. The input threshold of the MCU
and the PSD devices may differ, causing the devices to enter and exit reset at different
times because of slow ramping of the signal. This may result in the PSD not being
operational when accessed by the MCU. It is recommended to drive both devices actively.
A supervisory device or a gate with hysteresis is recommended.
t(s) For low-voltage ZPSD3XXV devices only, the reset input must be asserted for at least
500 nsec. The ZPSD3XXV will not be functional for an additional 500 nsec after reset is
uc de-asserted (see Figure 8). These low voltage ZPSD3XXV devices must use an active-low
d polarity signal for reset. Unlike the standard PSDs, the reset polarity for the ZPSD3XXV is
ro ) not programmable. If your MCU operates with an active high reset, you must invert this
P t(s signal before driving the ZPSD3XXV reset input.
te c You must design your system to ensure that the PSD comes out of reset and the PSD is
le u active before the MCU makes its first access to PSD memory. Depending on the
so rod characteristics and speed of your MCU, a delay between the PSD reset and the MCU reset
may be needed.
- Ob te P Table 8A. External PSD Signal States During and Just After Reset
) le Signal State Just
t(s so Signal State After Reset
c b Port
Configured Mode of Operation During Reset
(Note 1)
u O AD0/A0-
rod - AD15/A15
lete P uct(s) Port Pins
so rod PA0-PA7
All
MCU I/O
Tracking
AD0/A0-AD7/A7
Latched Address Out
Obbsolete PPort Pins
O PB0-PB7
MCU I/O
Chip Select Outputs,
CS0-CS7, CMOS
PSD3XX,
ZPSD3XX
ZPSD3XXV
PSD3XX,
ZPSD3XX
ZPSD3XXV
Input (Hi-Z)
Input (Hi-Z)
Input (Hi-Z)
Logic 0
Hi-Z
Input (Hi-Z
Logic 1
Hi-Z
MCU address
and/or data
Input (Hi-Z)
Active Track
Mode
MCU address
MCU address
Input (Hi-Z)
Per CS equations
Per CS equations
Chip Select Outputs,
PSD3XX,
ZPSD3XX
Hi-Z
Per CS equations
CS0-CS7, Open Drain
ZPSD3XXV
Hi-Z
Per CS equations
Address or Logic Inputs, A16-A18
Input (Hi-Z)
Input (Hi-Z)
Port Pins
PC0-PC2
Chip Select Outputs,
CS8-CS10, CMOS
PSD3XX,
ZPSD3XX
ZPSD3XXV
Logic 1
Hi-Z
Per CS equations
Per CS equations
NOTE: 1. Signal is valid immediately after reset for PSD3XX and ZPSD3XX devices. ZPSD3XXV devices need an
additional 500 nsec after reset before signal is valid.
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