PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
FIGURE 10-1:
PIC32MX1XX/2XX/5XX USB INTERFACE DIAGRAM
OSC1
OSC2
(PB Out)(1)
VBUS
USBEN
USB Suspend
CPU Clock Not POSC
Sleep
FRC
Oscillator
8 MHz Typical
TUN<5:0>(3)
Primary Oscillator
(POSC)
UFIN(4)
Div x
UPLLIDIV(5)
USB Suspend
PLL
Div 2
UFRCEN(2)
UPLLEN(5)
To Clock Generator for Core and Peripherals
Sleep or Idle
USB Module
Nominal +5V
SRP Charge
SRP Discharge
USB
Voltage
Comparators
48 MHz USB Clock(6)
Full Speed Pull-up
D+
Host Pull-down
Low Speed Pull-up
Transceiver
Registers
and
Control
Interface
SIE
D-
USBID(7)
VBUSON(7)
Host Pull-down
ID Pull-up
DMA
System
RAM
VUSB3V3
Transceiver Power 3.3V
Note 1:
2:
3:
4:
5:
6:
7:
PB clock is only available on this pin for select EC modes.
This bit field is contained in the OSCCON register.
This bit field is contained in the OSCTRM register.
USB PLL UFIN requirements: 4 MHz.
This bit field is contained in the DEVCFG2 register.
A 48 MHz clock is required for proper USB operation.
Pins can be used as GPIO when the USB module is disabled or if the USB is enabled but
DEVCFG3<31:30> = ‘0b00.
DS60001290E-page 106
2014-2017 Microchip Technology Inc.