PIC32MX150F256L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX150F256L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 10-10: U1STAT: USB STATUS REGISTER

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4

U-0

U-0

U-0

U-0

31:24

—

—

—

—

U-0

U-0

U-0

U-0

23:16

—

—

—

—

U-0

U-0

U-0

U-0

15:8

—

—

—

—

R-x

R-x

R-x

R-x

7:0

ENDPT<3:0>

Bit

27/19/11/3

U-0

—

U-0

—

U-0

—

R-x

DIR

Bit

26/18/10/2

U-0

—

U-0

—

U-0

—

R-x

PPBI

Bit

25/17/9/1

U-0

—

U-0

—

U-0

—

U-0

—

Bit

24/16/8/0

U-0

—

U-0

—

U-0

—

U-0

—

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits

(Represents the number of the BDT, updated by the last USB transfer.)

1111 = Endpoint 15

1110 = Endpoint 14

•

•

•

0001 = Endpoint 1

0000 = Endpoint 0

bit 3 DIR: Last BD Direction Indicator bit

1 = Last transaction was a transmit transfer (TX)

0 = Last transaction was a receive transfer (RX)

bit 2 PPBI: Ping-Pong BD Pointer Indicator bit

1 = The last transaction was to the ODD BD bank

0 = The last transaction was to the EVEN BD bank

bit 1-0 Unimplemented: Read as ‘0’

Note:

The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only

valid when the TRNIF bit (U1IR<3>) is active. Clearing the TRNIF bit advances the FIFO. Data in register

is invalid when the TRNIF bit = 0.

DS60001290E-page 120

 2014-2017 Microchip Technology Inc.

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