PIC32MX530F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX530F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

11.0 I/O PORTS

Note:

This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 12. “I/O Ports”

(DS60001120) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

General purpose I/O pins are the simplest of peripher-

als. They allow the PIC® MCU to monitor and control

other devices. To add flexibility and functionality, some

pins are multiplexed with alternate functions. These

functions depend on which peripheral features are on

the device. In general, when a peripheral is functioning,

that pin may not be used as a general purpose I/O pin.

The following are the key features of this module:

• Individual output pin open-drain enable or disable

• Individual input pin weak pull-up and pull-down

• Monitor selective inputs and generate interrupt

when change in pin state is detected

• Operation during CPU Sleep and Idle modes

• Fast bit manipulation using CLR, SET and INV

registers

Figure 11-1 illustrates a block diagram of a typical

multiplexed I/O port.

FIGURE 11-1:

BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE

PIO Module

RD ODC

Peripheral Module

Peripheral Module Enable

Peripheral Output Enable

Peripheral Output Data

Data Bus

SYSCLK

WR ODC

RD TRIS

WR TRIS

WR LAT

WR PORT

D

Q

CK

ODC

EN Q

1

0

0

1

D

Q

CK

TRIS

1

EN Q

0

D

Q

CK

LAT

EN Q

Output Multiplexers

I/O Cell

I/O Pin

RD LAT

1

RD PORT

0

Sleep

SYSCLK

Peripheral Input

R

Peripheral Input Buffer

Q

D

Q CK

Q

D

Q CK

Synchronization

Legend:

Note:

R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.

This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure

for any specific port/peripheral combination may be different than shown here.

 2014-2017 Microchip Technology Inc.

DS60001290E-page 129

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