TABLE 22-1: ADC REGISTER MAP (CONTINUED)
Bits
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
9100 ADC1BUF9 31:16
15:0
ADC Result Word 9 (ADC1BUF9<31:0>)
0000
0000
9110
ADC1BUFA
31:16
15:0
ADC Result Word A (ADC1BUFA<31:0>)
0000
0000
9120
ADC1BUFB
31:16
15:0
ADC Result Word B (ADC1BUFB<31:0>)
0000
0000
9130
ADC1BUFC
31:16
15:0
ADC Result Word C (ADC1BUFC<31:0>)
0000
0000
31:16
9140 ADC1BUFD 15:0
ADC Result Word D (ADC1BUFD<31:0>)
0000
0000
9150
ADC1BUFE
31:16
15:0
ADC Result Word E (ADC1BUFE<31:0>)
0000
0000
9160
ADC1BUFF
31:16
15:0
ADC Result Word F (ADC1BUFF<31:0>)
0000
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
2:
3:
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for details.
For 64-pin devices, the MSB of these bits is not available.
For 64-pin devices, only the CSSL30:CSSL0 bits are available.