PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
FIGURE 31-4:
POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
Power-up Sequence
(Note 2)
(TSYSDLY)
SY02
SY00
(TPU)
(Note 1)
CPU Starts Fetching Code
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR
Power-up Sequence
(Note 2)
SY00
(TPU)
(Note 1)
(TSYSDLY)
SY02
SY10
(TOST)
CPU Starts Fetching Code
Note 1:
2:
The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
Includes interval voltage regulator stabilization delay.
2014-2017 Microchip Technology Inc.
DS60001290E-page 325