PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC32MX230F128L-I/PF
Microchip Technology
PIC32MX230F128L-I/PF Datasheet PDF : 382 Pages
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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
Revision D (April 2016)
This revision includes the following major changes,
which are referenced by their respective chapter in
Table A-2.
TABLE A-3: MAJOR SECTION UPDATES
Section Name
Update Description
1.0 “Device Overview”
Removed the USBOEN pin and all trace-related pins from the Pinout I/O
Descriptions (see Table 1-1).
2.0 “Guidelines for Getting Started
with 32-bit MCUs”
3.0 “CPU”
Section 2.7 “Trace” was removed.
Section 2.10 “Sosc Design Recommendation” was removed.
References to the Shadow Register Set (SRS), which is not supported by
PIC32MX1XX/2XX/5XX 64/100-pin Family devices, were removed from
3.1 “Features”, 3.2.1 “Execution Unit”, and Coprocessor 0 Registers
(Table 3-2).
4.0 “Memory Organization”
5.0 “Interrupt Controller”
The SFR Memory Map was added (see Table 4-1).
The Single Vector Shadow Register Set (SSO) bit (INTCON<16>) was
removed (see Register 5-1).
10.0 “USB On-The-Go (OTG)”
23.0 “Controller Area Network
(CAN)”
The UOEMON bit (U1CNFG1<6>) was removed (see Register 10-20).
The CAN features (number of messages and FIFOs) were updated.
The PIC32 CAN Block Diagram was updated (see Figure 23-1).
The following registers were updated:
• C1FSTAT (see Register 23-6)
• C1RXOVF (see Register 23-7)
• C1RXFn (see Register 23-14)
• C1FIFOCONn (see Register 23-16)
• C1FIFOINTn (see Register 23-17)
• C1FIFOUAn (see Register 23-18)
• C1FIFOCIn (see Register 23-19)
The C1FLTCON4 through C1FLTCON7 registers were removed.
28.0 “Special Features”
31.0 “40 MHz Electrical
Characteristics”
The virtual addresses for the Device Configuration Word registers were
updated (see Table 28-1).
The EJTAG Timing Characteristics diagram was updated (see Figure 31-23).
DS60001290E-page 376
2014-2017 Microchip Technology Inc.
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