PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

4.0 MEMORY ORGANIZATION

Note:

This data sheet summarizes the features

of the PIC32MX1XX/2XX/5XX 64/100-pin

family of devices. It is not intended to be a

comprehensive reference source.For

detailed information, refer to Section 3.

“Memory Organization” (DS60001115)

in the “PIC32 Family Reference Manual”,

which is available from the Microchip

web site (www.microchip.com/PIC32).

PIC32MX1XX/2XX/5XX 64/100-pin microcontrollers

provide 4 GB of unified virtual memory address space.

All memory regions, including program, data memory,

SFRs and Configuration registers, reside in this

address space at their respective unique addresses.

The program and data memories can be optionally par-

titioned into user and kernel memories. In addition, the

data memory can be made executable, allowing

PIC32MX1XX/2XX/5XX 64/100-pin devices to execute

from data memory.

The key features include:

• 32-bit native data width

• Separate User (KUSEG) and Kernel (KSEG0/

KSEG1) mode address space

• Flexible program Flash memory partitioning

• Flexible data RAM partitioning for data and

program space

• Separate boot Flash memory for protected code

• Robust bus exception handling to intercept 

runaway code

• Simple memory mapping with Fixed Mapping

Translation (FMT) unit

4.1 Memory Layout

PIC32MX1XX/2XX/5XX 64/100-pin microcontrollers

implement two address schemes: virtual and physical.

All hardware resources, such as program memory,

data memory and peripherals, are located at their

respective physical addresses. Virtual addresses are

exclusively used by the CPU to fetch and execute

instructions as well as access peripherals. Physical

addresses are used by bus master peripherals, such as

DMA and the Flash controller, that access memory

independently of the CPU.

The memory maps for the PIC32MX1XX/2XX/5XX 64/

100-pin devices are illustrated in Figure 4-1 through

Figure 4-4.

 2014-2017 Microchip Technology Inc.

DS60001290E-page 39

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