LNBS21PD(2002) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

LNBS21PD
(Rev.:2002)

LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE

STMicroelectronics 

LNBS21

- no acknowledge, stopping the read mode

communication.

While the whole register is read back by the µP,

only the two read-only bits OLF and OTF convey

di-agnostic informations about the LNBS21.

PCL ISEL TEN LLC VSEL EN OTF OLF

Function

0

These bits are read exactly the same as 1

they were left after last write operation

Values are typical unless otherwise specified

TJ<140°C, normal operation

TJ>150°C, power block disabled, Loothrough switch open

0 IOUT<IOMAX, normal operation

1 IOUT>IOMAX, overload protection triggered

POWER-ON I2C INTERFACE RESET

The I2C interface built in the LNBS21 is

automatically reset at power-on. As long as the

Vcc stays be-low the UnderVoltage Lockout

threshold (6.7V typ.), the interface will not respond

to any I2C com-mand and the System Register

(SR) is initialised to all zeroes, thus keeping the

power blocks disabled. Once the Vcc rises above

7.3V, the I2C interface becomes operative and the

SR can be configured by the main µP. This is due

to About 500mV of hysteresis provided in the UVL

threshold to avoid false retriggering of the

Power-On reset circuit.

DiSEqCTM IMPLEMENTATION

The LNBS21 helps the system designer to

implement the bi-directional (2.x) DiSEqC protocol

by al-lowing an easy PWK modulation/

demodulation of the 22KHz carrier. The PWK data

are exchanged between the LNBS21 and the

main µP using logic levels that are compatible with

both 3.3 and 5V mi-crocontrollers. This data

exchange is made through two dedicated pins,

DSQIN and DSQOUT, in or-der to maintain the

timing relationships between the PWK data and

the PWK modulation as accurate as possible.

These two pins should be directly connected to

two I/O pins of the µP, thus leaving to the resident

firmware the task of encoding and decoding the

PWK data in accordance to the DiSEqC pro-tocol.

Full compliance of the system to the specification

is thus not implied by the bare use of the LNBS21.

The system designer should also take in

consideration the bus hardware requirements,

that include the source impedance of the Master

Transmitter measured at 22KHz. To limit the

attenuation at car-rier frequency, this impedance

has to be 15ohm at 22KHz, dropping to zero ohm

at DC to allow the power flow towards the

peripherals. This can be simply accomplished by

the LR termination put on the OUT pin of the

LNBS, as shown in the Typical Application Circuit

on page 5.

Unidirectional (1.x) DiSEqC and non-DiSEqC

systems normally don't need this termination, and

the OUT pin can be directly connected to the LNB

supply port of the Tuner. There is also no need of

Tone Decoding, thus, it is recommended to

connect the DETIN and DSQOUT pins to ground

to avoid EMI.

ADDRESS PIN

Connecting this pin to GND the Chip I2C interface

address is 0001000, but, it is possible to choice

among 4 different addresses simply setting this

pin at 4 fixed voltage levels (see table on page

10).

ELECTRICAL CHARACTERISTICS FOR LNBS SERIES (TJ = 0 to 85°C, EN=1, LLC=0, TEN=0, ISEL=0,

PCL=0, DSQIN=0, VIN=12V, IOUT=50mA, unless otherwise specified. See software description section

for I2C access to the system register)

Symbol

Parameter

VIN

VLT1

IIN

Supply Voltage

LT1 Input Voltage

Supply Current

VO Output Voltage

VO Output Voltage

Test Conditions

IO = 750 mA TEN=VSEL=LLC=1

IO = 0mA TEN=VSEL=LLC=1

IO = 750 mA VSEL=1

IO = 750 mA VSEL=0

EN=1

EN=0

LLC=0

LLC=1

LLC=0

LLC=1

Min. Typ. Max. Unit

8

15

V

20

V

20

40

mA

2.5

5

mA

17.3 18 18.7

V

19

V

12.5 13 13.5

V

14

V

8/19

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