STM8AF6288TCX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM8AF6288TCX
STMicroelectronics
STM8AF6288TCX Datasheet PDF : 125 Pages
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Option bytes
9
Option bytes
STM8AF526x/8x/Ax STM8AF6269/8x/Ax
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Each option
byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented
one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 18: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be changed in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 18. Option bytes
Addr.
Option
name
Option
byte
no.
7
6
5
Option bits
4
3
2
1
Factory
default
0 setting
0x00
4800
0x00
4801
0x00
4802
0x00
4803
0x00
4804
Read-out
protection
(ROP)
OPT0
User boot
code
(UBC)
OPT1
NOPT1
ROP[7:0]
UBC[7:0]
NUBC[7:0]
Alternate
function
remapping
(AFR)
OPT2
NOPT2
AFR7 AFR6 AFR5 AFR4 AFR3
NAFR7 NAFR6 NAFR5 NAFR4 NAFR3
AFR2
NAFR2
AFR1
NAFR1
AFR0
NAFR0
0x00
0x00
0xFF
0x00
0xFF
0x00
4805
0x00
4806
Watchdog
option
OPT3
NOPT3
0x00
4807
0x00
4808
Clock
option
OPT4
NOPT4
Reserved
Reserved
Reserved
Reserved
LSI_ IWDG WWD WWDG
EN _HW G _HW _HALT
NLSI_ NIWD NWWD NWWG
EN G_HW G_HW _HALT
EXT
CLK
CKAW
USEL
PRSC1 PRSC0
NEXT
CLK
NCKAW
USEL
NPRSC1
NPRSC
0
0x00
0xFF
0x00
0xFF
0x00
4809
0x00
480A
HSE clock
startup
OPT5
NOPT5
HSECNT[7:0]
NHSECNT[7:0]
0x00
0xFF
54/125
DocID14395 Rev 15
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