STM32F100RB(2010) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM32F100RB
(Rev.:2010)
(Rev.:2010)
STMicroelectronics
STM32F100RB Datasheet PDF : 84 Pages
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Electrical characteristics
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Table 41. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
VDDA
VREF+
IVREF
fADC
fS(2)
Power supply
Positive reference voltage
Current on the VREF input
pin
ADC clock frequency
Sampling rate
fTRIG(2) External trigger frequency
VAIN(3) Conversion voltage range
fADC = 12 MHz
2.4
3.6
V
2.4
VDDA
V
160(1) 220(1)
µA
0.6
0.05
0 (VSSA tied to
ground)
10
1
823
17
VREF+
MHz
MHz
kHz
1/fADC
V
RAIN(2) External input impedance
RADC(2) Sampling switch resistance
CADC(2)
Internal sample and hold
capacitor
tCAL(2) Calibration time
tlat(2)
Injection trigger conversion
latency
tlatr(2)
Regular trigger conversion
latency
tS(2) Sampling time
tSTAB(2) Power-up time
tCONV(2)
Total conversion time
(including sampling time)
See Equation 1 and
Table 42 for details
fADC = 12 MHz
fADC = 12 MHz
fADC = 12 MHz
fADC = 12 MHz
fADC = 12 MHz
50
k
1
k
8
pF
5.9
83
0.214
3(4)
0.143
2(4)
0.125
17.1
1.5
239.5
0
0
1
1.17
21
14 to 252 (tS for sampling +12.5 for
successive approximation)
µs
1/fADC
µs
1/fADC
µs
1/fADC
µs
1/fADC
µs
µs
1/fADC
1. Based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
3. In devices delivered in LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA),
see Table 4: STM32F100xx pin definitions and Figure 6.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41.
Equation 1: RAIN max formula:
RAIN
----------------------------T----S-----------------------------
fADC CADC ln 2N + 2
–
RADC
66/84
Doc ID 16455 Rev 2
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