STM32F100V8 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F100V8

Low & medium-density value line, advanced ARM®-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

STMicroelectronics 

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

5.3.13 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 34 are derived from tests

performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL

compliant.

Table 34. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Standard I/O input low

level voltage

VIL I/O FT(1) input low

level voltage

Standard I/O input

high level voltage

VIH I/O FT(1) input high

level voltage

Standard I/O Schmitt

Vhys

trigger voltage

hysteresis(2)

I/O FT Schmitt trigger

voltage hysteresis(2)

-

VDD > 2 V

VDD ≤2 V

-

–0.3

- 0.28*(VDD–2 V)+0.8 V

–0.3

- 0.32*(VDD–2 V)+0.75 V

V

0.41*(VDD–2 V) +1.3 V -

VDD+0.3

5.5

0.42*(VDD–2)+1 V

-

5.2

200

-

-

mV

5% VDD(3)

-

-

mV

Ilkg

Input leakage

current(4)

VSS ≤VIN ≤VDD

Standard I/Os

VIN = 5 V

I/O FT

-

-

-

-

±1

µA

3

RPU

Weak pull-up

equivalent resistor(5)

VIN = VSS

30

40

50

kΩ

RPD

Weak pull-down

equivalent resistor(5)

VIN = VDD

30

40

50

kΩ

CIO I/O pin capacitance

-

-

5

-

pF

1. FT = 5V tolerant. To sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled.

2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5.

Pull-up and pull-down resistors are designed with

PMOS/NMOS contribution to the series resistance is

ma itnriumeumres(~is1ta0n%ceoridnesre).ries

with

a

switchable

PMOS/NMOS.

This

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 22 and Figure 23 for standard I/Os, and

in Figure 24 and Figure 25 for 5 V tolerant I/Os.

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