STM32F100V8H6BTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM32F100V8H6BTR
STMicroelectronics
STM32F100V8H6BTR Datasheet PDF : 96 Pages
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Electrical characteristics
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 8.
Refer to Section 5.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 41. SPI characteristics
Symbol
Parameter
Conditions
Min
Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
Slave mode
-
12
-
12
MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
30
70
%
tsu(NSS)(1) NSS setup time
Slave mode
4tPCLK
-
th(NSS)(1) NSS hold time
Slave mode
2tPCLK
-
ttww((SSCCKKHL))((11)) SCK high and low time
Master mode, fPCLK = 24 MHz,
presc = 4
50
60
ttssuu((MSII))((11))
Data input setup time
Master mode
Slave mode
5
-
5
-
th(MI) (1)
th(SI)(1)
ta(SO)(1)(2)
Data input hold time
Master mode
Slave mode
Data output access time Slave mode, fPCLK = 24 MHz
5
-
4
-
ns
0
3tPCLK
tdis(SO)(1)(3) Data output disable time Slave mode
2
10
tv(SO) (1) Data output valid time Slave mode (after enable edge)
-
25
tv(MO)(1)
Data output valid time
Master mode (after enable
edge)
-
5
th(SO)(1)
Slave mode (after enable edge) 15
-
th(MO)(1) Data output hold time
Master mode (after enable
edge)
2
-
1. Guaranteed by characterization results.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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DocID16455 Rev 9
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