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STM8S208RB View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
STM8S208RB Datasheet PDF : 103 Pages
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Block diagram
3
Block diagram
STM8S207xx, STM8S208xx
Figure 1. STM8S20xxx performance line block diagram
Reset
Single wire
debug interf.
400 Kbit/s
10 Mbit/s
LIN master
SPI emul.
Master/slave
autosynchro
1 Mbit/s
16 channels
1/2/4 kHz
beep
Reset block
Reset
POR/PDR
BOR
Clock controller
Detector
XTAL 1-24 MHz
RC int. 16 MHz
RC int. 128 kHz
Clock to peripherals and core
STM8 core
Debug/SWIM
I2C
SPI
UART1
UART3
beCAN
ADC2
Beeper
Window WDG
Independent WDG
Up to 128 Kbytes
high density program
Flash
Up to 2 Kbytes
data EEPROM
Up to 6 Kbytes
RAM
Boot ROM
16-bit advanced control
timer (TIM1)
16-bit general purpose
timers (TIM2, TIM3)
8-bit basic timer
(TIM4)
Up to
4 CAPCOM
channels
+ 3 complementary
outputs
Up to
5 CAPCOM
channels
AWU timer
12/103
1. Legend:
ADC: Analog-to-digital converter
beCAN: Controller area network
BOR: Brownout reset
I²C: Inter-integrated circuit multimaster interface
Independent WDG: Independent watchdog
POR/PDR: Power on reset / power down reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
UART: Universal asynchronous receiver transmitter
Window WDG: Window watchdog
Doc ID 14733 Rev 12

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