Memory and register map
STM8S207xx, STM8S208xx
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
Address
Block
Register Label
Register Name
0x00 7F98
DM_CSR1
DM debug module control/status register 1
0x00 7F99
DM
DM_CSR2
DM debug module control/status register 2
0x00 7F9A
DM_ENFCTR
DM enable function register
0x00 7F9B to
0x00 7F9F
Reserved area (5 bytes)
1. Accessible by debug module only
2. Product dependent value, see Figure 8: Memory map.
Reset
Status
0x10
0x00
0xFF
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Doc ID 14733 Rev 12