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STM8S207S8T3C View Datasheet(PDF) - STMicroelectronics

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STM8S207S8T3C Datasheet PDF : 103 Pages
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Electrical characteristics
STM8S207xx, STM8S208xx
10.3.10
10-bit ADC characteristics
Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise
specified.
Table 44. ADC characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
fADC ADC clock frequency
VDDA = 3 to 5.5 V
1
VDDA = 4.5 to 5.5 V
1
4
MHz
6
VDDA Analog supply
3
5.5
V
VREF+ Positive reference voltage
2.75(1)
VDDA
V
VREF- Negative reference voltage
VSSA
0.5(1)
V
VAIN Conversion voltage range(2)
CADC
Internal sample and hold
capacitor
Devices with external
VREF+/VREF- pins
VSSA
VREF-
VDDA
V
VREF+
V
3
pF
tS(2) Sampling time
tSTAB Wakeup time from standby
tCONV
Total conversion time (including
sampling time, 10-bit resolution)
fADC = 4 MHz
fADC = 6 MHz
fADC = 4 MHz
fADC = 6 MHz
0.75
0.5
7
3.5
2.33
14
µs
µs
µs
µs
1/fADC
1. Data guaranteed by design, not tested in production..
2. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
82/103
Doc ID 14733 Rev 12

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