STM6600, STM6601
DC and AC characteristics
Symbol
Table 5. DC and AC characteristics (continued)
Parameter
Test condition(1)
Min.
Typ.(2)
Max. Unit
CSRD
ISRD CSRD charging current
100
150
200 nA
VSRD CSRD voltage threshold
tSRD
Additional Smart Reset™
delay time
VCC = 3.6 V, load on VREF pin
100 kΩ and mandatory 1 µF
capacitor, TA = 25 °C
External CSRD connected
1.5
V
10
s/µF
EN, EN
VOL Output low voltage
VCC = 2 V, ISINK = 1 mA,
enable asserted
0.3 V
VOH(5) Output high voltage
VCC = 2 V, ISOURCE = 1 mA,
enable asserted
VCC – 0.3
tEN_OFF(6) enable off to enable on
VCC ≥ 2.0 V
40
64
EN, EN leakage current
VEN = 2 V, enable open drain
–0.1
RST
VOL Output low voltage
VCC = 2 V, ISINK = 1 mA,
RST asserted
V
88 ms
+0.1 µA
0.3 V
tREC
INT
RST pulse width
RST leakage current
VCC ≥ 2.0 V
VRST = 3V
240
360
480 ms
–0.1
+0.1 µA
VOL Output low voltage
VCC = 2 V, ISINK = 1 mA,
INT asserted
0.3 V
tINT_Min Minimum INT pulse width
INT leakage current
VREF
VREF 1.5 V voltage reference
VCC ≥ 2.0 V
VINT = 3 V
VCC = 3.6 V, load on VREF pin
100 kΩ and mandatory 1 µF
capacitor, TA = 25 °C
20
–0.1
1.485
–1%
32
44 ms
+0.1 µA
1.5
1.515
+1%
V
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 1.6 V to 5.5 V (except where noted).
2. Typical values are at TA = +25 °C.
3. This blanking time allows the processor to start up correctly (see Figure 7, 8, 9, 10, 11, 12).
4. The internal pull-up resistor connected to the SR input is optional (see Table 10 for detailed device options).
5. Valid for push-pull only.
6. Minimum delay time between enable deassertion and enable reassertion, allowing the application to complete the power-down
properly. PB is ignored during this period.
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