MCP79521-I/SL View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
MCP79521-I/SL Datasheet PDF : 54 Pages
| |||
MCP795W1X/MCP795W2X
9.1.10 DATA PROTECTION
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A Write Enable instruction must be issued to set
the write enable latch
• After a byte write, page write, unique ID write, or
STATUS register write, the write enable latch is
reset
FIGURE 9-7:
CLRWDT
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal EEPROM
write cycle is ignored and programming is
continued
• Block protect bits are ignored for UID writes
9.1.11 CLEAR WATCHDOG INSTRUCTION
The Clear Watchdog command resets the internal
Watchdog Timer.
CS
SCK
01234567
SI
01000100
High-Impedance
SO
9.1.12 CLEAR RAM INSTRUCTION
The Clear Ram instruction is a 2-byte command that
will reset the internal SRAM to the known value. Using
this command, all locations in the SRAM are set to 00h
and the data value contained in the second byte of the
command is ignored.
FIGURE 9-8:
CLRRAM
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
Data
0 1 0 1 0 1 0 0 A7 6 5 4 3 2 1 A0
High-Impedance
DS22280C-page 36
Preliminary
2011-2012 Microchip Technology Inc.
Share Link: 