PIC24HJ128GP802-I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC24HJ128GP802-I/ML

High-Performance, 16-bit Microcontrollers

Microchip Technology 

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)

Section Name

Update Description

Section 10.0 “Power-Saving

Features”

Section 11.0 “I/O Ports”

Added the following registers:

• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)

• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)

• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)

Removed Table 11-1 and added reference to pin diagrams for I/O pin

availability and functionality.

Added paragraph on ADPCFG register default values to Section 11.3

“Configuring Analog Port Pins”.

Section 16.0 “Serial Peripheral

Interface (SPI)”

Section 18.0 “Universal

Asynchronous Receiver Transmitter

(UART)”

Section 19.0 “Enhanced CAN

(ECAN™) Module”

Section 20.0 “10-bit/12-bit Analog-to-

Digital Converter (ADC1)”

Added Note box regarding PPS functionality with input mapping to

Section 11.6.2.1 “Input Mapping”.

Added Note 2 and 3 to the SPIxCON1 register (see Register 16-2).

Updated the Notes in the UxMode register (see Register 18-1).

Updated the UTXINV bit settings in the UxSTA register (see

Register 18-2).

Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved

(see Register 19-1).

Replaced the ADC1 Module Block Diagrams with new diagrams (see

Figure 20-1 and Figure 20-2).

Updated bit values for ADCS<7:0> and added Notes 1 and 2 to the ADC1

Control Register 3 (AD1CON3) (see Register 20-3).

Added Note 2 to the ADC1 Input Scan Select Register Low (AD1CSSL)

(see Register 20-7).

Section 21.0 “Comparator Module”

Section 22.0 “Real-Time Clock and

Calendar (RTCC)”

Section 25.0 “Special Features”

Added Note 2 to the ADC1 Port Configuration Register Low (AD1PCFGL)

(see Register 20-8).

Updated the Comparator Voltage Reference Block Diagram

(see Figure 21-2).

Updated the minimum positive adjust value for CAL<7:0> in the RTCC

Calibration and Configuration (RCFGCAL) Register (see Register 22-1).

Added Note 1 to the Device Configuration Register Map (see Table 25-1).

Updated Note 1 in the PIC24H Configuration Bits Description (see

Table 25-2).

DS70293D-page 346

Preliminary

© 2009 Microchip Technology Inc.

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