ATSAM3N4BA-MU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAM3N4BA-MU

ARM-based Flash MCU

Atmel Corporation 

10.13 Chip Identification

• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.

Table 10-1. SAM3N Chip ID Register

Chip Name

ATSAM3N4C (Rev A)

ATSAM3N2C (Rev A)

ATSAM3N1C (Rev A)

ATSAM3N4B (Rev A)

ATSAM3N2B (Rev A)

ATSAM3N1B (Rev A)

ATSAM3N4A (Rev A)

ATSAM3N2A (Rev A)

ATSAM3N1A (Rev A)

• JTAG ID: 0x05B2E03F

CHIPID_CIDR

0x29540960

0x29590760

0x29580560

0x29440960

0x29490760

0x29480560

0x29340960

0x29390760

0x29380560

CHIPID_EXID

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

10.14 UART

• Two-pin UART

– Implemented features are 100% compatible with the standard Atmel USART

– Independent receiver and transmitter with a common programmable Baud Rate

Generator

– Even, Odd, Mark or Space Parity Generation

– Parity, Framing and Overrun Error Detection

– Automatic Echo, Local Loopback and Remote Loopback Channel Modes

– Support for two PDC channels with connection to receiver and transmitter

10.15 PIO Controllers

• 3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79

I/O Lines

• Each PIO Controller controls up to 32 programmable I/O Lines

• Fully programmable through Set/Clear Registers

Table 10-2. PIO available according to pin count

Version

48 pin

PIOA

21

PIOB

13

PIOC

-

64 pin

32

15

-

100 pin

32

15

32

• Multiplexing of four peripheral functions per I/O Line

• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)

– Input change, rising edge, falling edge, low level and level interrupt

– Debouncing and Glitch filter

40 SAM3N Summary

11011BS–ATARM–22-Feb-12

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