AT90PWM2B-16SU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT90PWM2B-16SU

8-bit Atmel Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

AT90PWM2/3/2B/3B

17.2.6

SPI Data Register – SPDR

Bit

Read/Write

Initial Value

7

SPD7

R/W

X

6

SPD6

R/W

X

5

SPD5

R/W

X

4

SPD4

R/W

X

3

SPD3

R/W

X

2

SPD2

R/W

X

1

SPD1

R/W

X

0

SPD0

R/W

X

SPDR

Undefined

• Bits 7:0 - SPD7:0: SPI Data

The SPI Data Register is a read/write register used for data transfer between the Register File

and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-

ter causes the Shift Register Receive buffer to be read.

17.3

Data Modes

There are four combinations of SCK phase and polarity with respect to serial data, which are

determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure

17-3 and Figure 17-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-

nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing

Table 17-2 and Table 17-3, as done below:

Table 17-5. CPOL Functionality

Leading Edge

CPOL=0, CPHA=0

Sample (Rising)

CPOL=0, CPHA=1

Setup (Rising)

CPOL=1, CPHA=0

Sample (Falling)

CPOL=1, CPHA=1

Setup (Falling)

Trailing eDge

Setup (Falling)

Sample (Falling)

Setup (Rising)

Sample (Rising)

SPI Mode

0

1

2

3

Figure 17-3. SPI Transfer Format with CPHA = 0

SCK (CPOL = 0)

mode 0

SCK (CPOL = 1)

mode 2

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0) MSB

LSB first (DORD = 1) LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

4317K–AVR–03/2013

183

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