4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Figure 25-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XTAL1
t XLXH
tXLPH
tPLXH
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 25-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-
ing operation.
Figure 25-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XTAL1
tXLOL
tBVDV
BS1
OE
tOLDV
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 25-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-
ing operation.
Table 25-14. Parallel Programming Characteristics, VCC = 5V ± 10%
Symbol
Parameter
Min Typ
VPP
IPP
tDVXH
tXLXH
tXHXL
tXLDX
tXLWL
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
11.5
67
200
150
67
0
Max
12.5
250
Units
V
A
ns
ns
ns
ns
ns
294