AT90PWM2B-16SU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT90PWM2B-16SU

8-bit Atmel Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

AT90PWM2/3/2B/3B

XCK, USART External clock. The Data Direction Register (DDD0) controls whether the clock is

output (DDD0 set) or input (DDD0 cleared). The XCK0 pin is active only when the USART oper-

ates in Synchronous mode.

SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an

input regardless of the setting of DDD0. As a slave, the SPI is activated when this pin is driven

low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD0.

When the pin is forced to be an input, the pull-up can still be controlled by the PORTD0 bit.

Table 11-10 and Table 11-11 relates the alternate functions of Port D to the overriding signals

shown in Figure 11-5 on page 67.

Table 11-10. Overriding Signals for Alternate Functions PD7..PD4

Signal Name

PD7/

ACMP0

PD6/ADC3/

ACMPM/INT0

PD5/ADC2/

ACMP2

PUOE

0

0

0

PUOV

0

0

0

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

AIO

0

0

0

0

ACMP0D

0

–

ACOMP0

0

0

0

0

ADC3D + In0en

In0en

INT0

ADC3

ACMPM

0

0

0

0

ADC2D

0

ADC2

ACOMP2

PD4/ADC1/RXD/

ICP1A/SCK_A

RXEN + SPE •

MSTR • SPIPS

PD4 •

PUD

RXEN + SPE •

MSTR • SPIPS

0

SPE • MSTR •

SPIPS

–

ADC1D

0

ICP1A

ADC1

77

4317K–AVR–03/2013

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